FIG. 12 is a block diagram schematically showing a liquid crystal display apparatus 1 of the TFT (Thin Film Transistor) active matrix, which is a typical liquid crystal display apparatus. The liquid crystal display apparatus 1 is basically provided with a liquid crystal panel 2 and a liquid crystal driving apparatus for driving the liquid crystal panel 2. The liquid crystal panel 2, which is a liquid crystal panel of the TFT type, is provided with liquid crystal display elements (not shown) and opposite electrode (common electrode) 3.
On the other hand, the liquid crystal driving apparatus 1 is provided with a source driver SD, a gate driver GD, a controller CTL, and a liquid crystal driving power source REG. The source driver SD and the gate driver GD are respectively provided with an IC (Integrate Circuit). In general, the source driver SD and the gate driver GD are mounted by (1) connecting a film, on which a wire is formed and the IC chip is mounted, such as a TCP (Tape Carrier Package), with an ITO (Indium Tin Oxide) terminal of the liquid crystal panel 2, or by (2) thermo compressing the IC chip directly on the ITO terminal of the liquid crystal panel 2, via an ACF (Anisotropic Conductive Film).
Moreover, in order to attain the miniaturization of the liquid crystal display apparatus, the controller CTL, the liquid crystal driving power source REG, the source driver SD and the gate driver GD may be constituted of a signal chip or a few (two or three) chips. In FIG. 12, those arrangements are separately illustrated in terms of functions.
The controller CTL outputs, to the gate driver GD and the source driver SD, digitalized display data (for example, RGB signals respectively corresponding to red, green, and blue) and various control signals. The control signals for the source driver SD are mainly a horizontal synchronizing signal, a start pulse signal, and a source driver clock signal (a clock signal for the source driver SD), and the like signals. The control signals for the source driver SD are indicated by the reference mark S1 in the figure, while the display data is indicated by the reference mark D. On the other hand, the control signals for the gate driver GD are mainly a vertical synchronizing signal, and a gate-driver clock signal (a clock signal for the gate driver GD), and the like signals. The control signals for the gate driver GD are indicated by the reference mark S2. Note that a power source for driving the ICs is omitted in the figure.
The liquid crystal driving power source REG supplies the source driver SD and the gate driver GD with a display voltage for causing the liquid crystal panel 2 to display (in the present invention, a reference voltage for generating a gradation display voltage). The display data D, which is inputted externally, is inputted into the source driver SD via the controller CTL, in a form of a digital signal. The source driver SD latches the inputted display data D into itself, in a time-division manner. Thereafter, the source driver SD carries out DA (digital/analog) conversion, synchronously to the horizontal synchronizing signal (which is also called as a latch signal) LS, which is inputted from the controller CTL. Thereby, analog display voltages for display (for displaying gradation) are obtained. The analog display voltages are outputted, as gradation display voltages, respectively to liquid display elements (not shown) inside the liquid crystal panel 2, the liquid display element corresponding to liquid crystal driving voltage output terminals.
FIG. 13 is an equivalent circuit diagram illustrating the liquid crystal panel 2. One of substrates of the liquid crystal panel 2 is sectioned into a matrix by a plurality of gate signal lines G1, G2, to Gn (a reference mark G is used when the plurality of gate signal lines G1, G2 to Gn are referred to), and a plurality of source signal lines S1, S2, to Sn (a reference mark S is used when the plurality of gate signal lines S1, S2 to Sn are referred to). By dividing the substrate into a matrix in this manner, regions A are formed. Each region A, which is for one pixel, is provided with a pixel electrode 11 and a TFT 12 as a switching element for turning ON or OFF voltage application onto the pixel electrode 11. The pixel electrode 11 and the opposite electrode 3, which is provided on the other substrate, form a pixel capacitor 14.
The source signal lines S receive, from the source driver SD, the gradation display voltages, which correspond to brightness of display-target pixels (pixels to be used for displaying a certain screen image to be display at that time), whereas the gate signal lines G receive scanning signals so as to turn ON the TFTs 12 lined up in a vertical direction from a position at which the gate driver GD is located. Via the TFTs 12 thus turned ON, the gradation display voltages of the source signal lines S are applied onto the pixel electrodes 11, which are connected to drains of the TFTs 12. In this way, the gradation display voltage is stored in the pixel capacitor 14 between the pixel electrode 11 and the opposite electrode 3. Thereby, light transmittance of liquid crystal between the pixel electrode 11 and the opposite electrode 3 is changed, so as to display.
FIGS. 14 and 15 are views illustrating examples of a liquid crystal driving waveform. In those figures, the reference mark S shows a waveform of the gradation display voltage from the source driver SD, while the reference mark G shows a waveform of the scanning signal from the gate driver GD. Moreover, the reference number 3 indicates a potential of the opposite electrode 3, whereas the reference number 11 shows a voltage waveform of the pixel electrode 11. A voltage applied onto a liquid crystal material is potential difference between the pixel electrode 11 and the opposite electrode 3. The voltage applied onto the liquid crystal material is indicated by slanting strokes.
For example, in FIG. 14, when the scanning signal (indicated by the reference mark G) from the gate driver GD is at a High level, the TFT 12 is turned ON, so that a difference between (a) the gradation display voltage (indicated by the reference mark S) from the source driver SD and (b) the potential of the opposite electrode 3 is applied into the pixel electrode 11. Thereafter, as the reference mark G indicates, the scanning signal from the gate driver GD becomes a Low level, so that the TFT 12 is turned OFF. Here, the voltage is maintained in the pixel, because of the presence of the pixel capacitor 14.
FIG. 15 shows a similar operation. However, the voltages applied onto the liquid crystal materials are different between FIGS. 14 and 15. In FIG. 14, the applied voltage is higher than in FIG. 15. The light transmittance of the liquid crystal is altered in an analog manner, by changing the voltage applied onto the liquid crystal to be an analog voltage in this way. Thereby, a multi-gradation display is realized. How many gradations can be displayed is dependent on how many discrete levels of analog voltages can be applied into the liquid crystal. The present invention relates to a reference voltage generating circuit and an output circuit in a gradation display circuit. The reference voltage generating circuit and the output circuit occupy a large area in the gradation display circuit, and consume a large electric power. Hereinafter, the liquid crystal driving apparatus is explained, mainly discussing the source driver SD.
FIG. 16 is a block diagram illustrating an arrangement of a typical conventional source driver 20 used as the source driver SD. Only basic parts of the source driver 20 are explained below. Digital display data DR, DG, and DB (for example in 6 bits) are transmitted from the controller CTL, and temporarily latched by an input latch circuit 21. Note that the digital display data DR, DG, and DB respectively correspond to red, green, and blue colors.
On the other hand, the start pulse signal SP, which is synchronized to the clock signal CK, is transmitted through a shift register circuit 22, and outputted, as a start pulse signal SP (cascade signal S), from a last stage of the shift register circuit 22 to a source driver, which is the next stage in the process. The digital display data DR, DG, and DB, which have been latched by the input latch circuit 21 synchronously to the output signals from the respective stages of the shift register circuit 22, are temporally stored in a sampling memory circuit 23 in a time-division manner, and are outputted to a hold-memory circuit 24, which is the next stage in the process.
When display data of one horizontal synchronizing period is stored in the sampling memory circuit 23 in this manner, the hold-memory circuit 24 accepts an output signal from the sampling memory circuit 23 in accordance with a horizontal synchronizing signal LS, and holds the display data until a next horizontal synchronizing signal LS is inputted. Conversion of an output signal from the hold-memory circuit 24, such as voltage boosting of the output signal, is carried out by a level shifter circuit 25 so as to be in conformity with a signal level of a DA converting circuit 26, which is the next stage in the process.
The DA converting circuit 26 selects one analog voltage from among a plurality of analog voltages from a reference voltage generating circuit 27 in accordance with the display data subjected to the level conversion by the level shifter circuit 25, and generates an applied voltage level (the gradation display voltage) to be applied into the liquid crystal panel 2. In accordance with a reference voltage VR from the liquid crystal driving power source REG, the reference voltage generating circuit 27 generates various analog voltages for the gradation display, and outputs the analogs voltages to the DA converting circuit 26. The analog voltage, which realizes the gradation display, is outputted as the gradation display voltage, from each liquid crystal driving voltage output terminal (hereinafter, just refereed to as an output terminal) 29 to each source signal line S via an output circuit 28. The output circuit 28 is basically a buffer circuit, and is realized by a voltage follower circuit using, for example, a differential amplification circuit.
Next, explained in detail are circuit arrangements of the reference voltage generating circuit 27 and the DA converting circuit 26, to which the present invention especially relate. FIG. 17 is a view illustrating the circuit arrangement of the reference voltage generating circuit 27. In case the digital display data corresponding to RGB are, for example, respectively in 6 bits, the reference voltage generating circuit 27 outputs analog voltages of 64 kinds, that is, V0 to V63, so as to deal with 64 (=26) kinds of gradation display respectively. In the following, the specific arrangement is explained.
The reference voltage generating circuit 27 has such a simple arrangement that the reference voltage generating circuit 27 is constituted by a resistance divided circuit in which resistances R0 to R7 are connected in series. Each of the resistances R0 to R7 is connected, in series, with eight (8) resistance elements. Specifically, for example, discussing about the resistance R0 by way of explanation, the resistance R0 is constituted by eight resistance elements R01, R02 to R08, which are connected in series, as shown in FIG. 18. Moreover, the other resistances R1 to R7 have the same arrangement as the resistance R0. Therefore, the reference voltage generating circuit 27 is constituted by 64 resistance elements in total, which are connected in series.
Moreover, the reference voltage generating circuit 27 includes nine (9) voltage input terminals that correspond to nine (9) kinds of references voltages V′0, V′8, to V′56, and V′64. Further, an end of the resistance R0 is connected with the voltage input terminal that corresponds to the reference voltage V′64, and the other end of the resistance R0, that is, a node between the resistances R0 and R1 is connected with the voltage input terminal that is for halftone and corresponds to the reference voltage V′56. (Hereinafter, the voltage input terminals that are for halftone are referred to as the halftone voltage input terminals.) Similarly, each node between the resistances next to each other is connected with the halftone voltage input terminal, that is, the nodes between the resistances R1 and R2, R2 and R3, to R6 and R7 are respectively connected with the halftone voltage input terminals that respectively correspond to the reference voltages V′48, V′40, to V′8. The other end of the resistance R7 is connected with the voltage input terminal that corresponds to the reference voltage V′0.
With those arrangements, it is possible to obtain the 63 kinds of analog voltages V1 to V63 respectively from nodes between pairs of the 64 resistance elements. This gives the 64 kinds of the analog voltages V0 to V63 for gradation display, by summing up the analog voltages V1 to V63 and the analog voltage V0 that is obtained from the reference voltage V′0 without such process. Where the reference voltage generating circuit 27 is constituted of a resistance divided circuit as described above, the analog voltages V0 to V63 are determined by differences between the resistances. The analog voltages V0 to V63 are inputted from the reference voltage generating circuit 27 to the DA converting circuit 26.
Note that, in general, there is a case where the two reference voltages located on the both ends, namely, V′0 and V′ 64, are inputted into the voltage input terminals all the time, whereas the 7 halftone voltage input terminals corresponding to the remaining reference voltages V′8 to V′56 are used for fine adjustment. Practically, there is a case where no voltage is inputted into those terminals.
Next, explained is the DA converting circuit 26. FIG. 19 is a view illustrating an example of an arrangement of the DA converting circuit 26. Note that the reference mark 28 indicates the arrangement of the output circuit 28 (voltage follower circuit) in the figure. The DA converting circuit 26, broadly speaking, includes a MOS transistor or a transmission gate as analog switches, so that one of the 64 kinds of analog voltages V0 to V63 thus inputted are selected in accordance with display data composed of digital signals Bit0 to Bit5 in 6 bits. In other words, the analog switches are turned ON or OFF in accordance with the display date composed of the digital signals Bit0 to Bit5 in 6 bits, respectively.
Hereinafter, this arrangement is explained in detail. As to the digital signals Bit0 to Bit5 in 6 bits, the digital signal Bit0 represents LSB, and the Bit5 represents MSB. The analog switches constitute switching pairs, which are two analog switches in pairs. The digital signal Bit0, which represents LSB, corresponds to thirty two (32) switching pairs (sixty four (64) analog switches SW0), while the digital signal Bit1 correspond to sixteen switching pairs (thirty two (32) analog switches SW1). Similarly, for the rest of the digital signals Bit2 to Bit5, as the reference number of bit is increased, a number of the analog switches corresponding to the digital signal are halved (in short, sixteen analog switches correspond to the digital signal Bit2, while 8 analog switches correspond to the digital signal Bit3). Thus, only a pair of analog switches (two analog switches) corresponds to the MSB digital signal Bit5. Therefore, in total, there are 63 pairs (32+16+8+4+2+1=63) of analog switching pairs (that is, 126 analog switches).
Ends of the analog switches SW0 that correspond to the digital signal Bit0 that represents LSB are terminals that receives the analog voltages V0 to V63 respectively. Further, the other end of the analog switches SW0 are connected in pairs, and connected to ends of the analog switches that correspond to the digital signal Bit1 that is next to the digital signal Bit0. The rest of the analog switches, including the analog switches SW5 corresponding to the MSB digital signal Bit5, are arranged in a similar manner, so that an other end (which corresponds to the other end of the analog switch SW0) of the analog switch SW5 is connected to the output circuit 28. The analog switches SW0 to SW5 are controlled in the following manner, in accordance with the digital signal Bit0 to Bit5 in 6 bits.
As to each of the analog switches SW0 to SW5, when its corresponding one of the digital signals Bit0 to Bit5 is “0” (Low level), one of the analog switches in pairs (in FIG. 19, lower one of the analog switches) is turned ON, whereas the other one of the analog switches (in FIG. 19, upper one of the analog switches) is turned ON when its corresponding one of the digital signals Bit0 to Bit5 are “1”. FIG. 19 illustrates a case where the display data described by the digital signals Bit0 to Bit5 is “111111”, thus all the upper switches are ON and all the lower switches are OFF for all the switching pairs. In this case, the analog voltage V63 is outputted from the DA converting circuit 26 to the output circuit 28. Similarly, for example if the display data is “111110”, the analog voltage V62 is outputted from the DA converting circuit 26 to the output circuit 28. When the display data is “000001”, the analog voltage V1 is outputted. The analog voltage V0 is outputted if the display data is “000000”. In this manner, one of the analog voltages V0 to V63 for gradation display is selected in accordance with the digital display data, so as to realize the gradation display.
In addition, in actual gradation display of the liquid crystal display apparatus, γ correction is carried out for adjusting differences between light transmittance characteristics of the liquid crystal material and visual characteristics of humans in order to perform natural gradation display. For the γ correction, it is a general method that the resistance elements are unevenly, that is, not evenly, divided in order that the reference voltage generating circuit 27 generates the analog voltages V0 to V63 for gradation display.
FIG. 20 is a graph showing a relationship between the display data composed of the digital signal Bit0 to Bit5 in the 6 bits and liquid crystal driving output voltages (the analog voltages V0 to V63), in case the γ correction is carried out. As shown in FIG. 20, the values of the analog voltages plotted with respect to the display data have polygonal characteristics. In order to realize the characteristics, the reference voltage generating circuit 27 shown in FIG. 17 carries out the γ correction by setting the ratio of the resistance values of the respective resistances R0 to R7 to be a ratio with which the γ correction can be realized.
In the conventional source driver 20 having the above arrangement, usually a single of the reference voltage generating circuit 27 is provided in one of IC chips in the source driver SD, for shared usage among the IC chips. On the other hand, the DA converting circuit 26 and the outputting circuit 28 are provided corresponding to each output terminal 29. Moreover, in case of color display, the output terminals 29 are used respectively corresponding to the colors. Thus, in this case, the DA converting circuit 26 and the output circuit 28 are provided to each color in each pixel. Specifically, where there are an N number of pixels along a longitudinal direction of the liquid crystal panel 2, and where R, G, B, indicates the colors, and associating number n (n=1, 2, to N), the output terminals 29 for the respective red, green and blue colors are marked as: R1, G1, and B1; R2, G2, and B2; to; RN, GN, and BN. Thus, a 3N number of the DA converting circuit 26 and the outputting circuit 28 are necessary.
Especially, the output circuit 28, which is as described above constituted by the differential amplifier, and which is an analog circuit, need a large layout area and consumes a large electric power. To provide the output circuit 28 to each output terminal 29 is a serious problem for a display apparatus for a portable apparatus, in which miniaturization and low electric power consumption are especially demanded.
On the other hand, even though it depends on an output impedance of the pixel capacitor 14, which is a load, and the resistances R0 to R7 of the reference voltage generating circuit 27, for a liquid crystal panel for a small or medium size, for example, of 560×240 pixels, it is possible to omit the output circuit 28, so as to output the liquid crystal driving voltage directly from the respective resistances R0 to R7 via the analog switches SW0 to SW5. However, since the liquid crystal driving electric power REG of low electric power consumption is provided, each voltage line for outputting the reference voltage VR to the reference voltage generating circuit 27 has a small current supplying ability. Because of this, when the output circuit 28 is omitted, such problems may be caused that a waveform of the liquid crystal driving voltage has non-sharp rising and falling edges, or that variation in voltage caused by charging and discharging the pixel capacitor 14 shifts γ characteristics described above, even if the resistance values of the respective resistances R0 to R7 are appropriately set.